1. Field of the Invention
The present invention relates to a multilayer printed wiring board and production method therefor, more particularly, to a multilayer printed wiring board having a structure of Interstitial Via Hole (hereinafter, referred to as “IVH”) and a manufacturing method thereof.
2. Description of the Related Art
A multilayer printed wiring board with a “through hole structure. Specifically, a multilayer printed wiring board with copper foil laminate and prepreg sheet material are integrally stacked one after the other on a build-up board and a plurality of holes (through holes) are formed in the thickness direction of the build-up board. Via the through holes, the front surface side conductor circuits and the rear surface side conductor circuits of a build-up board and/or one or both of the above circuits and conductor circuits on an interlayer within the build-up board are electrically connected. However, there resides the following drawback; i.e., the area for forming the through holes has to be provided, thus this hampers the approach for high density mounting of component parts.
Consequently, a multilayer printed wiring board with IVH structure suitable for high density mounting, particularly a multilayer printed wiring board with any layer IVH structure attracts attention. In the multi layer printed wiring board with any layer IVH structure, in each of the insulation layers constituting a build-up board, via holes are provided for electrically interconnecting between the conductor circuits. That is, in this type of multilayer printed wiring board, interlayer conductor circuits or an interlayer conductor circuit and a front/rear surface conductor circuit are electrically connected therebetween by means of via holes (also named as buried via hole or blind via hole), which do not penetrate the wiring board, and allows flexible layout of electrical connection paths in the interlayer.
FIGS. 10(a)-10(e) show a manufacturing process chart of a conventional IVH structured multilayer printed wiring board (refer to, for example, Japanese Laid-Open Patent Application (Kokai) (A) No. 2000-101248, or Japanese Laid-Open Patent Application (Kokai) (A) No. 2000-183528). In this process, as seen in FIG. 10(a) first of all, a prepreg 1, in which an aramid nonwoven fabric is impregnated with epoxy resin, is drilled to form a predetermined number of holes for via holes 1a, and each of the holes for via holes 1a is filled with conductive paste or electrolytic plating 2. Then, as seen in FIG. 10(b), the both sides of the prepreg 1 are overlapped with copper foils 3, 4 and heat pressed. Thereby, the epoxy resin of the prepreg 1 and the conductive paste or electrolytic plating 2 filled in the hole for via holes 1a come into contact with each other and integrate entirely; and thus, the copper foils 3, 4 on the both sides of the prepreg 1 are electrically connected via the conductive paste or electrolytic plating 2. Then, as seen in FIG. 10(c), the copper foils 3, 4 are subjected to a patterning into a desired configuration. Thus, a hard double-sided substrate 9 is obtained including via holes 7 and 8 (hardened conductive paste or electrolytic plating 2) that electrically connect the conductive circuits 5 and 6 (patterned copper foils 3 and 4) on the both sides.
When the double-sided substrate 9, which is formed as described above, is multilayered as a core layer into, for example, a 4 layered print wiring board, as seen in FIG. 10(d), prepregs 11 filled with conductive paste or electrolytic plating 10 are positioned and built up in order on both sides of the double-sided substrate 9.
However, as the above-described conventional art, when the conductive paste or electrolytic plating 2 is used as filling material of the holes for via holes 1a, there may be a case where the amount of filling of the conductive paste or electrolytic plating 2 in each of the holes for via holes 1a is different. Therefore, for example, as shown in FIG. 11(a), when the amount of filling is too much, a swell 17 is generated on the exposed surfaces of the via hole 16 formed in the prepreg 15. Or, as shown in FIG. 11(b), when the amount of filling is short, a recession 18 is generated on the exposed surface of the via holes 16. As a result, there resides such a problem that, when the adjacent layers are built up and heat pressed, due to the influence of the swell 17 or the recession 18, the thickness of the adjacent layers (thickness of insulation film) is undesirably changed. Needless to say, when the amount of filling is precisely controlled, such disadvantage is not caused. However, precise control of the amount of filling leads to an increase of the management man-hour in the manufacturing process resulting in an increase of manufacturing cost.